The customer demands are the latest ARM instruction set issued for the customers, and the
developing of a set of processor simulation assessment platform based on the instruction set is just to support the high-speed function simulator and the timing precision-level performance simulation,and support the SMT/SMP, the Cache/DDR and the latest consistent agreements,and other functions, etc. so as to guide the development of the software and hardware of processor ARMv8, to help them quickly occupy the market and improve the embedded system service of the latest high-performance.
SmartSimu - HPA simulator supports the latest ARM instruction set, and can be used for the timing model of the performance evaluation of the clock-accurate out-of-order pipelines. The model supports the functions of the dynamic scheduling algorithm, the multi-issue instruction-fetching decoding, the Tournament branch prediction and so on , the rapid adjustment of execution unit number, the extension module of coprocessor/accelerator , SMT and SMP, etc.
SmartSimu - HPA provides two kinds of simulation models, the function simulation model and the performance simulation model.The function simulation simulates the ARM instruction set by the way of dynamic binary translation, which makes the function simulation speed more close to the speed of the real hardware. After the simulator starts, the functional simulation model is first initiated to parse the input parameters and configure the corresponding content, and thenthe user programs are loaded, the translation executed, and the exception handling and system calls and other functions are supported. The performance simulation model completely simulates the out-of-order core pipelines, the multi-issue, the Tomasolu algorithm, the Tournament branch prediction method, the Cache module, DDRC module, SMT, SMP, etc, and also provides the rich performance statistics.
The simulation speed of the performance Simulator can reach up to 200 kips and the functional simulation speed up to 200 MIPS, and the performances are superior to other commercial simulators.
The chart of function modules is shown as following:
1. The dynamic binary translation acceleration
Slow simulation speed has been one of the bottlenecks for the further development of the simulators.
For the problem, and in the function simulation mode, SmartSimu - HPA accelerates the speed by the method of dynamic binary translation, which supports the latest ARM instruction set, and the contents completes includes the definitions of ARM instruction set, decoding tree, GR and floating point registers, exception handling, dynamic binary translation and the realization of the system calls, etc. Through the usage of dynamic binary translation mechanism, the function simulation speed can reach more than 200 MIPS.
2. accurate timing simulation of clock
Through the function of Tomasolu algorithm, the functional units such as reservation station and ROB have realized the out-of-order core pipelines prototype .The component phases of the pipelines adopt the high modularization and configurability, and the issue widths of the pipelines,the sizes of the reservation stations, all the sizes of associated queues, the sizes of submitted widths and the branch prediction models are all adjustable. The instruction translation of the performance simulation module adopts the optimized way of Basic Block, and can greatly reduce the valuing and decoding time and significantly improve the execution speed of the line rows, and the instruction execution speed can reach 200 k/s.
3. The Cache simulation
Implement two cache simulations: the simple cache and the consistent cache.
The simple cache is used to create the single core cache or the shared cache in the cases of multi-core running circumstance.
The consistent cache is used to simulate the private cache in the cases of multi-core, and has realized the two kinds of protocols: the msci and the moesi. The msci protocol uses the snoop listening mode, and the moesi uses the way of the directory.
4. The SMP/SMT simulation
The simulator supports the SMP simulation with the maximum of 256 cores, and each core supports the SMT simulation with 8 threads.
5. DDR access and storage interface simulation
SmartSimu - HPA supports DRAM simulator of the third-party integrated, such as the mature simulator DRAMsim2, and the access and storage interface simulation has simulated the most of the modern elements in the main memory system, for example, the Ranks, Banks, command queue and the storage controller, etc.
The main features of the products :
Complete functions: Support the latest ARM instruction set; Support SMP simulation with the maximum of 256 cores ,and each core supports the SMT simulation with 8 threads ; Supports the simulation of the timing-level pipeline architecture; Support the whole running of the system.
High speed: The function simulator can reach up to 200 MIPS; The timing precision-level performance simulation can reach up to 200 kips; The execution of dhrystone can achieve 3 DMIPS/MHz.
Flexible configurations: Support the two kinds of simulation model,the quick function simulation model and the timing-accurate simulation model, and support to quickly switch; Support the rich and configurable data statistics and output, and can meet the rapid assessment requirements of high performance processor architectures of the out-of-order super variable structures.